Peter Ramm



Peter Ramm’s and Mitsumasa Koyanagi’s efforts in developing, demonstrating, and commercializing 3D integrated circuit (3DIC) integration processes have played a key role in enabling ever-smaller yet more-powerful devices especially important to mobile communications. 3D integration and packaging involves stacking silicon wafers and interconnecting them vertically so that they behave as a single device, which achieves performance at reduced power and with a smaller footprint than conventional 2D processes. Ramm developed and patented 3D integration approaches with particular focus on die-to-wafer stacking, using low-temperature bonding and vertical integration of IC devices with TSVs, and demonstrated a complete industrial 3DIC integration process. He also published results on key processes such as 3D metallization including robust IMC interconnections and on advanced sensor applications of 3D heterogeneous integration.

An IEEE Senior member, Ramm is the head of Strategic Projects at Fraunhofer EMFT, Munich, Bavaria, Germany.