Hideo Sunami, Mitsumasa Koyanagi and Kiyoo Itoh are responsible for three of the major milestones in the evolution of modern dynamic random access memories (DRAMs). Their development of trench and stacked capacitor cells and folded data line cells resulted in unmatched high signal-to-noise ratio. Today, three decades after their invention, these cells remain the de facto standard for the DRAM industry.
In 1976, Dr. Koyanagi devised the stacked capacity cell, the dominant DRAM cell since the 1-Mb generation came into being. His work has stimulated research and development on a variety of stacked capacitor cell structures,capacitor insulators and capacitor electrode structures, including those using hemispherical grain, high-k material and metal/insulator/metal. His work has also been successfully applied to other memory devices with three-dimensional stacked structures, such as ferroelectric RAM (FRAM). He is currently a professor in the Department of Bioengineering and Robotics, Tohoku University in Sendai, Japan.
Mitsumasa Koyanagi’s and Peter Ramm’s efforts in developing, demonstrating, and commercializing 3D integrated circuit (3DIC) won them the IEEE Electronics Packaging Award. Koyanagi succeeded in fabricating 3D stacked image sensor, 3D stacked memory, and 3D stacked microprocessor test chips using through-silicon vias (TSVs) for the first time. He also demonstrated a four-layer stacked image sensor with quarter video graphics array resolution, a four-layer stacked multicore processor, and a four-layer stacked heterogeneous image sensor with extremely high frame rate.
An IEEE Fellow, Dr. Koyanagi is the recipient of the IEEE Cledo Brunetti Award, SSDM Award of the International Conference on Solid-State Devices and Materials, Commendation by the Ministry of Education, Culture, Sports, Science and Technology - Person of science and technological merits (Japan),and the Okochi Memorial Technology Prize.