First Commercial Digital Signal Processor Chip, 1980
In 1980, NEC (formerly Nippon Electric Company) developed here the first commercially available, programmable digital signal processor chip, the μPD7720. Its novel bus structure, 250-nsec instruction cycle, and 16-bit multiplier enabled fast finite impulse response filtering and provided true real-time processing for complex systems. It accelerated the adoption of digital signal processing in communications and broadcasting.
Street address(es) and GPS coordinates of the Milestone Plaque Sites
1753 Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa, 211-8666, Japan 35.57254306° N, 139.66515449° E 1753 Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa, 211-8666, Japan 35.57254306° N, 139.66515449° E
Details of the physical location of the plaque
The milestone plaque will be placed at the visitor entrance of the North and the South Building, Tamagawa Plant, NEC Corporation. The location is an area open to public during office hours so that anybody can see the milestone plaque.
How the intended plaque site is protected/secured
The intended plaque site is in a building located in NEC Tamagawa Plant. Security guards watch but visitors can freely visit there during office hours.
Historical significance of the work
PD7720 is the first “commercially available” digital signal processor (DSP) chip in the world. It was presented at IEEE International Solid-State Circuits Conference (ISSCC)  and IEEE International Conference on Acoustic, Speech, and Signal Processing (ICASSP)  in 1980. In the same session of these conferences, another DSP developed by AT&T Bell Laboratories was presented [3, 4]. PD7720 was released in the market in 1980 [5-11] before the AT&T chip became available as DSP-20 only for AT&T’s internal use . Texas Instruments (TI), which is recognized as the leader in the DSP market, announced its first DSP, TMS32010, in 1982 [13, 14]. However, it was necessary to wait for two more years until TMS32010 was released in the market until 1984 . PD7720 had been the only DSP commercially available in the market until TMS32010 was released.
PD7720 was used to implement an ADPCM (adaptive differential pulse code modulation) codec of a palm size . Because the tiny ADPCM codec board significantly impressed the ICASSP attendees, NEC was invited to join ITU-T (formerly CCITT) ADPCM standardization. In the course of standardization including evaluation by hardware, the flexibility (programmability) of PD7720 greatly helped establish the standard algorithm in the short period as originally planned. The resulting ADPCM standard includes floating-point multiplication which could not be implemented by the conventional DSPs. PD7720 was modified to make a new DSP, PD7730, with an 8x8 bit multiplier and a barrel shifter to implement floating-point multiplication essential to the ITU-T ADPCM standard [16, 17].
Because PD7720 had been available in the market since 1980 [5, 10, 11], there were a wide range of users in the world. The first user was Massachusetts Institute of Technology (MIT) whose paper on vocoder (low-bitrate speech encoder) first presented in May 1982  and published with extensions in February 1983 . μPD7720 was also used in speech synthesis  in those days. The biggest market for μPD7720 was modems  where an EPROM (erasable programmable ROM) version, μPD77P20 announced in 1981, was often used and the peak market share was over 90% . A DSP with efficient pipeline operations suitable for modems was also developed in 1982 based on μPD7720 . This chip allowed multiprocessor connection with no external logic. In the late 1980s, a shrunk CMOS version with an 8 MHz clock and an extended RAM, μPD77C25, was put in the market. μPD7720 is the origin of these descendent DSPs in the following years for various applications.
μPD7720 as well as its family chips enabled realtime signal processing in the 1980s, leading to cost reduction and spreading of technology based on signal processing. Included, but not limited to, are digital transmission signal modulation, speech, audio, and video coding, speech recognition/synthesis, signal enhancement/interference cancellation to name a few. From a viewpoint of products, telecommunication equipment such as switches and transmission terminals, multimedia players such as Walkman, mobile phone handset including smartphones, digital cameras and camcorders, digital TV receivers, car navigation systems, DVD recorders/players, PCs and tablet PCs are implemented by DSPs or DSP cores. We cannot live for a second without digital signal processors.
Features that set this work apart from similar achievements
Their commercial availability and fast multiplication with a novel data bus structure. Close collaboration between the research laboratory and the product division made μPD7720 commercially available soon after its announcement in 1980 [5, 10, 11], whereas AT&T’s DSP-20 was made available only within the company . TI’s TMS32010 came into the market a couple of years later than μPD7720 . Worldwide researchers and engineers benefit from flexibility of μPD7720 and its family chips, including an EPROM version announced in 1981, through quick prototyping of their algorithms and evaluation in realtime .
Compared to AT&T’s DSP-20, μPD7720 provides four-fold speedy multiplication due to single-clock multiplication capability [1, 2, 11, 26], leading to the true realtime processing for complex systems. A single-clock 16x16 bit multiplication, completed within a single instruction cycle of 250 nsec, and faster FIR (finite impulse response) filtering, which is one of the most common operations in signal processing including Fourier Transform, were significant advantages of NEC’s μPD7720. DSP-20 had a 4x20-bit partial multiplier and needs four times the instruction cycle, totaling 800 nsec to complete 16x20-bit multiplication [4, 27].
The fast multiplication of μPD7720 was made available by a 16x16-bit full multiplier and a novel multi-bus structure [1, 2, 11, 26]. Two input data could be supplied with the multiplier simultaneously via different buses so that it was not necessary to wait for the other data to arrive in the next instruction cycle [11, 26]. A novel data pointer structure, which consists of a 3-bit modifier register and a 4-bit counter, replaced time-consuming data transfers in the tapped delay line of an FIR filter through the bus with a ring buffer and its start address shift. The 3-bit modifier register enabled a jump to one of the eight pages of the RAM and the 4-bit counter enabled a sequential access to continuous memory addresses in the tapped delay line.
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2. T. Nishitani, Y. Kawakami, R. Maruta, A. Sawai, “LSI signal processor development for communications equipment,” Proc. ICASSP80, pp. 386-389, April 1980.
3. J. R. Boddie, G. T. Daryanani, I. I. Eldumiati, R. N. Gadenz, J. S. Thompson, S. M. Walters, and R. A. Pedersen, “A digital signal processor for telecommunications applications,” Digest of Tech. Papers, ISSCC, WAM 3.4, pp.44-45, Feb. 1980.
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8. “Telecom-specific microcomputer developed by NEC: Single-chip and high-speed,” Denki Shimbun (Electrical News), Feb. 14, 1980. (in Japanese)
9. “NEC developed a telecom-specific single-chip microcomputer: At a price of 20K Yen,” Dempa Shimbun (Radio News), Feb. 18, 1980. (in Japanese)
10. NEC “μPD7720 Digital Signal Processing Interface,” Data Sheet, 1981.
11. R. Maruta, “At the dawn of the digital signal processing era, My association with Dr. Takao Nishitani,” IEEE Solid-State Circuits Magazine, Vol. 9, Issue 2, pp.25-29, Spring 2017.
12. T. Nishitani, “The advent of DSP and its growth in human society – Part 1,” IEICE Fundamental Review, Vol. 1, No. 4, pp. 17-29, Apr. 2008. (in Japanese)
13. S. S. Magar, E. R. Caudel, and A. W. Leigh, “A microcomputer with digital signal processing capability,” Digest of Tech. Papers, ISSCC, WAM 2.5, pp. 32-33, 284-285, Feb. 1982.
14. E. R. Caudel, R. K. Hester, and K-S. Tan, “A chip set for audio frequency digital signal processing,” Proc. ICASSP, pp. 1065-1068, April 1982.
15. T. Nishitani, S. Aikoh, T. Araseki, K. Ozawa, and R. Maruta, “A 32 kb/s toll quality ADPCM codec using a single chip signal processor”, Proc. of ICASSP, pp.960-963, April 1982.
16. M. Sato, Y. lshikawa, T. Nishitani, T. Kato, H. Saita, and Y. Aoki, “A single chip signal processor for CCITT standard ADPCM codec,” Digest of ISSCC, THPM 14.7, pp. 192-193, Feb. 1985.
17. T. Nishitani, I. Kuroda, M. Satoh, T. Katoh, R. Fukuda and Y. Aoki, “A CCITT standard 32 kbps ADPCM LSI codec”, Proc. of ICASSP, pp.1425-1428, April 1985.
18. J. A. Feldman, "A compact digital channel vocoder using commercial devices," ICASSP 1982, Vol. 7, pp1960-1963, May 1982.
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20. D. J. Quarmby and J. N. Holmes, “Implementation of a parallel-formant speech synthesizer using a single-chip programmable signal processor,” IEE Proceedings F, Vol. 131, Issue 6, pp. 563-569, Oct. 1984.
21. R. W. Cain, “Microprocessor Based 9600 BPS Modem,” Proc. ICASSP1985, 42.9, pp. 1633-1636, Apr. 1985.
22. Y. Kawakami, “Development of a digital signal processor,” Journal of the Society of Semiconductor Industry Specialists, No. 75, pp. 13-16, Apr. 2012. (in Japanese)
23. M. Yano, K. Inoue, and T. Senba, “An LSI digital signal processor,” Proc. ICASSP1982, pp. 1073-1076, May 1982.
24. T. Nishitani, “Two-term vector multiplier,” USP4215417, July 29, 1980 (Filed Jan. 27, 1978 [JP]).
25. T. Nishitani, “Sampled data processing system having memory with areas alternately dedicated to data I/O and data processing,” USP4287558, September 1, 1981 (Filed Sep. 29, 1977 [JP]).
26. T. Nishitani, R. Maruta, Y. Kawakami, H. Goto, “A single-chip digital signal processor for telecommunication applications,” IEEE J. of Solid-State Circuits, Vol. SC-16, No. 4, pp. 372-376, August 1981.
27. J. Boddie, “A brief history of AT&T’s first digital signal processor, Technology challenges in its development,” IEEE Solid-State Circuits Magazine, Vol. 9, Issue 2, pp.14-18, Spring 2017.
A. A. Sengupta, “Takao Nishitani and John S. Thompson receive the 2017 IEEE Donald O. Pederson Award in Solid-State Circuits,” IEEE Solid-State Circuits Magazine, Vol. 9, Issue 1, pp.65-66, Winter 2017.
B. R. Jain, “The 2017 IEEE Donald O. Pederson Award Winners,” IEEE Solid-State Circuits Magazine, Vol. 9, Issue 2, pp. 13 and 40, Spring 2017.
C. K. K. Parhi, “Takao Nishitani, An outstanding researcher, technical leader, and mentor,” IEEE Solid-State Circuits Magazine, Vol. 9, Issue 2, pp. 35-37, Spring 2017.
D. H. Harasaki, “Real-time programmable DSPs for video processing, The challenges of their development,” IEEE Solid-State Circuits Magazine, Vol. 9, Issue 2, pp.30-34, Spring 2017.
E. A picture of μPD7720 and μPD77P20.