Ian A. Young
- IEEE Frederik Philips Award
Ian A. Young revolutionized the design of microprocessor clocking circuitry by designing Phase Locked Loop (or PLL) clocking circuits that drove the performance of Intel Pentium and Intel Core processors from 50 MHz to over 3 GHz. This innovation contributed to the rapid increase in the speed performance of microprocessors through the 1990s while following Moore’s Law scaling. PLL clocking circuits are among the most-used analog components within microprocessor integrated circuit products. As a manager of SRAM design and analog circuit design teams, Young developed a “Process Development & Circuit Design Co-optimization Methodology” to optimize the microprocessor performance, process density, and yield. This co-optimization methodology has become a standard across the semiconductor industry to date.
An IEEE Life Fellow, Young is a senior fellow and Director of Exploratory Integrated Circuits at Intel Corporation, Hillsboro, OR, USA.