Ernest Yue Wu
- IEEE Cledo Brunetti Award
James H. Stathis’ and Ernest Yue Wu’s expertise of gate dielectric reliability has permitted circuit designers to push transistor performance to the limit by continuing dielectric scaling while maintaining operation voltage sufficient to deliver high drive current integral to today’s smaller yet more powerful devices. Their work has provided the ability to accurately predict the oxide lifetime at use conditions from accelerated stress data at elevated voltages, which has been essential as oxide thickness has scaled from ~10 nm to ~1 nm. Wu developed a power-law model for voltage dependence of gate oxide breakdown that profoundly changed the landscape for semiconductor scaling. Building on the progressive breakdown concept, he created a failure-current-based methodology that led to a comprehensive understanding of transistor failure.
An IEEE Fellow, Wu is a senior technical staff member with IBM Research, Essex Junction, Vermont, USA.