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RISC-I chip, die area 77 mm2, includes 44,420 transistors. Small block at upper right is the central processing unit, implementing 31 instructions. Lower left block is a register file of 78 dual-port 32-bit registers. Blocks at top left and lower right provide selective access to the registers for reading and writing. Technology employed was metal-gate NMOS with a minimum feature size of 5 micrometers.<br />[[Media:Dave&Carlo.jpg|Dave&Carlo.jpg]] | RISC-I chip, die area 77 mm2, includes 44,420 transistors. Small block at upper right is the central processing unit, implementing 31 instructions. Lower left block is a register file of 78 dual-port 32-bit registers. Blocks at top left and lower right provide selective access to the registers for reading and writing. Technology employed was metal-gate NMOS with a minimum feature size of 5 micrometers.<br />[[Media:Dave&Carlo.jpg|Dave&Carlo.jpg]]<br />[[Media:RISC1group.jpg|RISC1group.jpg]] |
Latest revision as of 18:25, 5 June 2013
RISC-I chip, die area 77 mm2, includes 44,420 transistors. Small block at upper right is the central processing unit, implementing 31 instructions. Lower left block is a register file of 78 dual-port 32-bit registers. Blocks at top left and lower right provide selective access to the registers for reading and writing. Technology employed was metal-gate NMOS with a minimum feature size of 5 micrometers.
Dave&Carlo.jpg
RISC1group.jpg
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current | 18:18, 5 June 2013 | 2,154 × 1,620 (1.95 MB) | Dahodges (talk | contribs) | RISC-I chip, die area 77 mm2, includes 44,420 transistors. Small block at upper right is the central processing unit, implementing 31 instructions. Lower left block is a register file of 78 dual-port 32-bit registers. Blocks at top left and lower right |
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